FPGA IP Core

High-Speed Data Interface for Simera Sense xScape Imagers

A lightweight, high-performance FPGA IP Core for direct integration with Simera Sense xScape imagers. Captures and converts high-speed image data streams into usable formats, enabling rapid deployment in satellite and edge processing systems.

Overview

One IP core. Complete data path.

The Zaitra XSCAPE Readout IP Core (ztr-core-xscape-rd) handles the entire data path from raw LVDS input to structured image output — with no CPU involvement during readout. Running in the programmable logic of AMD Zynq™ UltraScale+™ MPSoC or Zynq™ 7000 SoCs, it processes incoming xScape data in real time using a single AXI4-Stream-based pipeline.


Pre-validated as part of the SKAIDOCK hardware integration with Simera Sense xScape imagers, the IP core is production-tested against the xScape Electrical Functional Model, representative of the full xScape100 and xScape200 product lines across all spectral configurations.

Key features

Built for real mission conditions

Plug-and-Play Integration


  • Fully compatible with all Simera Sense xScape imager variants — xScape100 and xScape200

  • Supports AMD Zynq™ UltraScale+™ MPSoC and Zynq™ 7000 SoC

  • Ready-to-use CLI application for fast deployment and testing

  • Verified with standard Xilinx AXI DMA IP Core — no custom DMA required

High-Speed Data Handling


  • Compatible with all imager data readout configurations up to 400 Mbps

  • Supports both SDR and DDR readout modes

  • Real-time packet parsing and image formatting with no buffering overhead

  • CRC-32 data integrity verification on every received packet, with automatic rejection and error status reporting

Standards-Compliant Architecture


  • AXI4-Lite control interface — register-mapped, CPU-accessible

  • AXI4-Stream data output — direct feed to Xilinx AXI DMA IP Core

  • Single IP core handles full data path from LVDS to memory

  • Minimal FPGA footprint: 1,087 LUTs, 1,770 Flip-Flops, 13 BRAM, 1 DSP

Software Integration


  • Supplied with a Python-based CLI for readout control and configuration

  • Automates band sequencing, readout timing, and metadata parsing

  • Full support for multi-band sensors with user-space orchestration

  • Distributed as part of the SKAIROOT embedded Linux distribution

Operation modes

Three output modes, selectable at runtime

Raw Packet Output

Raw xScape packets are forwarded verbatim to the AXI4-Stream interface.

Binary Raw Image

Incoming xScape packets are parsed and pixel data is assembled into a flat binary image output in little-endian byte order.

TIFF with Metadata

The core generates a fully-compliant TIFF bitstream in real time. The TIFF header is constructed from session metadata.

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Resources

Get a closer look

Download the datasheet and explore the XSCAPE Readout IP Core in detail.

XSCAPE Readout FPGA IP Core Datasheet

pdf, 44 KB

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